Design and Implementation of a Multicast Router for Network-on-Chip Architectures

• Main Authors: Zhi-Hong Ye, 葉志宏
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/91389296780948225998

碩士 === 國立東華大學 === 資訊工程學系 === 99 === Owing to the ever advancing of semiconductor technology, system-on-chip (SoC) design is more and more important since a large number of homogeneous or heterogeneous silicon intellectual property blocks can be integrated as a system. As the system size grows in complexity, the on-chip interconnection network has become a critical issue due to problems such as noise, power dissipation, and reliability. Thus, it has been proposed that a packet-switched network delivering messages between communicating components is a viable solution for the SoC interconnect problem. Such architecture is called network-on-chip (NoC). The irregular network is an important topology for NoC architectures since it provides great flexibility for the on-chip interconnection with various IP block sizes and diverse application requirements. We have proposed the tree-based routing architecture for irregular networks called TRAIN, which achieves deadlock freedom and high-throughput and low-latency communication for NoC. With TRAIN, a packet arriving in a switch can be adaptively routed to utilize a shortcut to reduce the distance to the destination switch efficiently. In this thesis, we study the multicast routing in a TRAIN router and propose two router designs: the unicast router and the multicast router. The aim is to improve network performance with cost-effective router design. The experimental results show that the multicast router achieves better network performance than the unicast router at reasonable cost. With the network size grows, the performance advantage will be more pronounced for the multicast router.