| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 99 === In this thesis, we propose a novel direct digital frequency synthesizer (DDFS) with an architecture based on the equi-section difference method. For such DDFS, the first quadrant of the sinusoid function is divided into a number of sections with equal width. It is based on the use of linear piecewise technique to approximate the waveform in each section.
The memory usage is first discussed and an analysis of the linear approximation error is derived. From this analysis, the upper bound and lower bound of maximum linear approximation error with respect to a given number of linear segments are provided.
We also propose another modified equi-section difference method for hardware implementation, with the merit of enhancing memory compression ratio further more. To validate the proposed DDFS architectures, they are implemented in the target device Altera Stratix II FPGA and measured with oscilloscope, logic analyzer, and spectrum analyzer. The simulation and implementation results show that the proposed architecture achieves a significantly better memory compression ratio compared with that of previously presented DDFS designs of similar performance.
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