A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block
碩士 === 國立中山大學 === 電機工程學系研究所 === 99 === In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpola...
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ndltd-TW-099NSYS54420712015-10-19T04:03:19Z http://ndltd.ncl.edu.tw/handle/54920445417497539170 A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block 基於線性插值與校正塊的直接數位頻率合成器 Shi-wei Chen 陳世瑋 碩士 國立中山大學 電機工程學系研究所 99 In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR). The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip’s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2. Chih-Wen Kuo Ju-Ya Chen 郭志文 陳儒雅 2011 學位論文 ; thesis 42 zh-TW |
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碩士 === 國立中山大學 === 電機工程學系研究所 === 99 === In this thesis, a linear interpolation direct digital frequency synthesizer (DDFS) with improved structure to simplify the hardware complexity by correction block is proposed. Correction block is mainly used to compensate for the error curve of linear interpolation DDFS. From the analysis of these error curves, these error curves have similar behavior between each others. After selecting an error curve, the other error curves can be derived and multiplied by a fixed scale. From the simulation results, the correction block using the above method can improve about 12 dB spurious frequency dynamic range (SFDR).
The goal of the DDFS designed in this thesis is to achieve 80 dB SFDR. Minimum required number of bits for each block in the proposed DDFS is carefully selected by simulation. In general, DDFS with piecewise linear interpolation theoretically needs 32 segments of piecewise linear interpolation to achieve 84 dB SFDR. In this thesis, 16 segments of piecewise linear interpolation with correction block can achieve the target SFDR. The chip’s simulation is implemented by TSMC standard 0.13um 1P8M CMOS process with core area 78.11 x 77.49 um2.
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author2 |
Chih-Wen Kuo |
author_facet |
Chih-Wen Kuo Shi-wei Chen 陳世瑋 |
author |
Shi-wei Chen 陳世瑋 |
spellingShingle |
Shi-wei Chen 陳世瑋 A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
author_sort |
Shi-wei Chen |
title |
A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
title_short |
A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
title_full |
A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
title_fullStr |
A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
title_full_unstemmed |
A Direct Digital Frequency Synthesizer based on Linear Interpolation with Correction Block |
title_sort |
direct digital frequency synthesizer based on linear interpolation with correction block |
publishDate |
2011 |
url |
http://ndltd.ncl.edu.tw/handle/54920445417497539170 |
work_keys_str_mv |
AT shiweichen adirectdigitalfrequencysynthesizerbasedonlinearinterpolationwithcorrectionblock AT chénshìwěi adirectdigitalfrequencysynthesizerbasedonlinearinterpolationwithcorrectionblock AT shiweichen jīyúxiànxìngchāzhíyǔxiàozhèngkuàidezhíjiēshùwèipínlǜhéchéngqì AT chénshìwěi jīyúxiànxìngchāzhíyǔxiàozhèngkuàidezhíjiēshùwèipínlǜhéchéngqì AT shiweichen directdigitalfrequencysynthesizerbasedonlinearinterpolationwithcorrectionblock AT chénshìwěi directdigitalfrequencysynthesizerbasedonlinearinterpolationwithcorrectionblock |
_version_ |
1718094143276711936 |