A Sub-threshold 7T SRAM with Single Bit-line Structure

• Main Authors: Lin, Kuo-Hua, 林國華
• Other Authors: Chang, Mi-Chang
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/07824522446282026610

碩士 === 國立清華大學 === 電機工程學系 === 99 === Scaling SRAM’s supply voltage to sub-threshold region greatly reduces power consumption. However, the conventional 6T SRAM cell does not operate in sub-threshold region well. Conventional 6T SRAM cell has three major issues for operating in sub-threshold region. The first one is low read SNM (static noise margin) with voltage decreased. The second one is worse write ability due to weak transistor current. The third one is leakage current may interfere the read operation. Therefore, many novel cells have been proposed to solve the issues for sub-threshold SRAM [5][9][11]. This work is based on one of these cells, the 10T cell [11]. A 10T cell solved these issues caused by sub-threshold operations. But it uses more area compared to other cells. We propose a cell that changes the differential structure of 10T cell to single-ended structure, thus, reduces the cell transistor number to 7. However, it has lower write ability. Therefore, boost word-line and cut-off feedback are added to help write ability. This cell is shown to have smaller leakage current compared to cell with similar area by simulation. It also has smaller area compared to 10T cells.