Fast Test Integration: Toward Plug-and-Play Embedded At-speed Test Framework for Multiple Clock Domains in System-On-Chips Based on IEEE Standard 1500
博士 === 國立清華大學 === 電機工程學系 === 99 === 隨著製程技術的不斷提升,晶片速度持續攀高,與時序(timing)相關的延遲缺陷(delay defects),例如電阻短路、電阻斷路或者是訊號完整性問題,也逐漸了主宰晶片測試的品質(test quality)。然而,以傳統偵測定值錯誤(Stuck-at fault)為主流的測試方法並無法有效的檢測出時序相關的延遲缺陷,因此無法驗證晶片是否能夠操作在設計規格(design specifications)所規範的功能時脈速度(functional clock speed) 。單單依靠傳統定值錯誤測試不僅僅降低測試效率也額外增加...
Main Authors: | Chen, Po-Lin, 陳柏霖 |
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Other Authors: | Chang, Tsin-Yuan |
Format: | Others |
Language: | en_US |
Published: |
2011
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Online Access: | http://ndltd.ncl.edu.tw/handle/68087992473847969806 |
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