| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 99 === Multiplier is an important component in the application of digital signal processing (DSP) systems. However, it is desirable to remain the same bit width for the multiplication in some applications. For this reason, fixed-width multipliers only keeps the most significant half part of the products and a large error would be produced. Thus, many compensation methods are provided to solve this problem.
In this research, an error compensation method for fixed-width two’s-complement array multipliers is proposed at first. According to the statistical analysis for the truncation term, a general form for different word width compensation circuit is made up. For the 8×8 fixed-width multiplier as an example, the proposed method achieve 15:65% accuracy comparison with Direct-t method. Also, the proposed multiplier has 41% savings in gate count comparison with post-truncation multiplier when it is implemented in a 0:18-um process. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs.
Then, a probabilistic estimation compensation (PEC) method for fixed-width Booth multiplier is presented. According to the probabilistic analysis for the truncation part, we
can obtain a formula to calculate the compensation value easily. In the application of long bit width, we can not only avoid the exhaustive simulation but also implement in a simple compensation circuit architecture with nice accuracy. Compared to the previous works, the proposed method achieve better performance. In order to verify the performance of PEC multipliers in real applications, an 8 × 8 two-dimensional (2-D) discrete cosine transform (DCT) is implemented in a 0:18-um process. The result shows that the proposed PEC method can save 23% area with 4dB peak signal-to-noise ratio (PSNR) penalty.
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