1.2V 10-bits Low Power Successive Approximation Register Analog-to-Digital Converter

• Main Authors: Chun-Fu Chen, 陳俊甫
• Other Authors: Chi-Chang Lu
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/494753

碩士 === 國立虎尾科技大學 === 電機工程研究所 === 99 === Recently, low power ADC has been developed for many energy-constrained applications, such as wireless sensor networks and bio-medical applications. Among many types of ADC, slope ADC, sigma-delta ADC, and successive approximation register ADC (SAR ADC) are good candidates for low power applications. SAR ADC has recently become very attractive due to their minimal active analog circuit requirements. SAR ADC consists of dual sampling capacitor, sample-and-hold circuit (S/H), digital-to-analog converter (DAC), comparator, and successive approximation register. Bootstrapped switch is applied to sample-and-hold circuit to achieve rail-to-rail signal swing at low-voltage power supply. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC. In this research, 10-bits 727kS/s SAR ADC under a single 1.2V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 57.5dB and SNDR of 56.3dB. The peak DNL is -0.7LSB ~ 0.95 LSB, the peak INL is -1.22LSB ~ 1.48LSB, and the power dissipation is about 21.9μW. Simulations have been performed to demonstrate the feasibility of this new technique.