DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS

• Main Authors: Wen-Jiun Huang, 黃文駿
• Other Authors: Yaw-Fu Jan
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/09055301273166765638

碩士 === 大同大學 === 電機工程學系(所) === 99 === In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer.