DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
碩士 === 大同大學 === 電機工程學系(所) === 99 === In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with on...
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ndltd-TW-099TTU054420182015-10-19T04:03:44Z http://ndltd.ncl.edu.tw/handle/09055301273166765638 DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS 全數位鎖相迴路設計 Wen-Jiun Huang 黃文駿 碩士 大同大學 電機工程學系(所) 99 In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer. Yaw-Fu Jan 詹耀福 2011 學位論文 ; thesis 56 en_US |
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碩士 === 大同大學 === 電機工程學系(所) === 99 === In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with only four reference clock. A ring-delay-line consisting of 32 stages makes it possible for both the frequency detector and DCO to have a common time base, resulting in this unique clock generator. The pulse delay circuit is connected in a ring shape with 32 inverters ( inverters).With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. The generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock for a high-speed response. The frequency synthesizers are developed by Verilog, and they are simulated by Modelsim to justify the feasibility of the proposed frequency synthesizer.
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author2 |
Yaw-Fu Jan |
author_facet |
Yaw-Fu Jan Wen-Jiun Huang 黃文駿 |
author |
Wen-Jiun Huang 黃文駿 |
spellingShingle |
Wen-Jiun Huang 黃文駿 DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
author_sort |
Wen-Jiun Huang |
title |
DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
title_short |
DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
title_full |
DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
title_fullStr |
DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
title_full_unstemmed |
DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS |
title_sort |
design of all digital phase-locked loop circuits |
publishDate |
2011 |
url |
http://ndltd.ncl.edu.tw/handle/09055301273166765638 |
work_keys_str_mv |
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