| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 99 === The popularization and rapid growth of portable electronic products results in that more and more attention has been paid to the high performance and low cost power manage projects. As a competitive kind of power management, the new generation of low dropout linear regulator (LDO) with ultra low noise, high PSRR, micro-power loss and the lowest cost will be holding an important position.
This thesis focuses on the design of a low dropout linear regulator (LDO) IC with improved stability. Not only lead to the reduction of the required PCB space and component cost, but also make the power management more efficient and reasonable. In order to improve efficiency, the PMOS transistor is adopted to achieve the low dropout voltage. The bypass circuit is designed to reduce the output voltage noise and improve power supply rejection, which make the chip adapt to audio devices. Furthermore, its fast start-up circuit is designed to reduce the start-up time. The circuit is added to ensure the stability in whole load range, improve the transient response and greatly reduce the cost of the application.
Based on the principle of LDO and TSMC 0.35um CMOS process, the whole chip and its sub-blocks have been designed and simulated using the EDA software, such as View Draw, Hspice and Laker. The results of simulation indicate that the dropout voltage is just 190.6mV at the condition of output current 150mA, and all of other characteristics meet the specification. The layout area is 1058μm x 947μm without I/O PADs.
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