| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 100 === With the great progress of the semiconductor technology, the operating frequency of ICs and the data rate of communication systems become faster and faster. However, the higher operating frequency and data rate will make more electromagnetic interference (EMI) effects. With EMI, the electronic devices will influence each other in high speed and work irregularly. There are many techniques proposed to solve the EMI problem. The spread spectrum clock generator (SSCG) is the hottest solution in all techniques. The SSCG is modulated with a spreading profile in traditional clock generators. The output frequency of the SSCG spreads out in a frequency range and achieves the spread spectrum. Comparing with other solutions for EMI, the SSCG has lower cost.
In addition, with SSCG, the data rate is no longer fixed but in a certain frequency range. The transmitter will produce additional jitter to the receiver, and the bit error rate of the receiver is increased accordingly. Hence, the spreading ratio of SSCG is always chosen in a small range, such as 5000ppm. However, if the transmitter can transmit data stream with a larger spreading ratio (>10%), there will be more EMI reduction. As a result, if the receiver can tolerance a larger spreading ratio, it is very useful for EMI reduction performance of the whole circuit.
In this thesis, we propose an all-digital clock and data recovery (CDR) with some features to overcome the large spreading ratio. The interpolator based fine tuning architecture of the digital controlled oscillator (DCO) overcomes the non-monotonic phenomenon of conventional cascaded DCO architecture. The adaptive control scheme and the time-to-digital converter (TDC) based fast phase compensation enhance the tracking ability of conventional CDR circuit with a large spreading ratio (>10%). In addition, the proposed ADCDR circuit performs fast lock-in and doesn’t need an reference clock, or a multi-phase clock generator and oversampling architecture. The area, power consumption and design complexity can be greatly reduced.
The chip of this thesis is implemented in 90nm CMOS process with standard cells, and thus it has good portability over different processes. The core area is 0.09mm2 and the power consumption is 4.28mW at 480MHz with 10% down spread.
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