| Summary: | 碩士 === 長庚大學 === 電機工程學系 === 100 === The primary function of the duty cycle corrector(DCC) is to correct the duty cycle to 50% from unbalanced duty cycle. Many applications such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Double-Sampling Analog-to-Digital Converters(Double-Sampling ADC), and Clock and Data Recovery (CDR),both rising and falling edges of the clock are utilized to double the data rate. In these applications, the duty cycle corrector plays an important role in maintaining the duty cycle at 50%.
This paper proposed a synchronous 50% all-digital duty-cycle corrector (ADDCC). The proposed ADDCC has many features, including fast-locked, a wider acceptable duty-cycle range of input clock, synchronizing output phase with input phase. The proposed ADDCC is implemented in a 0.18-μmCMOS process. The circuit can operate from 500 to 900 MHz, and accommodates a wide range of input duty cycle ranging from 15% to 85%. The duty-cycle error of the output signal is less than 2.7%. The RMS and peak-to-peak jitters are 1.9 ps and 14.7 ps at 900MHz, respectively. The circuit operated from a 1.8-V supply voltage, the circuit dissipates 7.3 mA at 900MHz. This fully-integrated DCC chip area is 0.55 mm × 0.7 mm, the core area is 0.2 mm × 0.25 mm.
|
|---|
