Design a High Performance On-chip Interconnection Network for Thousand Many-core Architecture

• Main Authors: Yan-Wen Peng, 彭彥文
• Other Authors: Slo-Li Chu
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/86722221034368896238

碩士 === 中原大學 === 資訊工程研究所 === 100 === The continuous improving of semiconductor technology makes more transisters fill into a single chip. Integrating multilple processor cores into a single chip is also a main orientation of developing computer architectures. While integtate more and more cores into a chip, the interconnection network of all of the cores become a main performance bottleneck. Conventional PCB-based interconnection networks are not suitable for on-chip network. Accordingly, this paper provides a new on-chip interconnection network, Selt Similar Cubic (SCC), for many-core architectures. By cooperating with proposed linking mechanism, routing algorithm, and switching architectures, SSC has better scalability, on-chip fabrication possibility, and high communication performance, than conventional on-chip networks, such as Mesh, Hypercube, Butterfly, Mesh-of-Trees, and Fat Tree. In this paper, the theoretical analysis of peroformance and area cost are proposed. Than the pratical examinations of SSC with other networks under different communication patterns are provided. The analysis and experimental results reveal that SSC can provide higher throughput and lower area cost than other on-chip networks. The performance per area cost of SSC is five times better than that of Mesh. Since the capabilities of SSC, it can support more than thounand cores into a single chip without modifing the swich architecture and routing mechanism.