| Summary: | 碩士 === 國立高雄應用科技大學 === 電子工程系 === 100 === Stress Induced Voiding (SIV) is also called Stress Migration (SM) which is one of most important reliability concerns for dual damascene Cu interconnection in the advance circuits. Continuous shrinking the dimensions of interconnections, the void is formed under the via when the via connects the wide metal with high aspect ratio. Stress is playing as the major dominator but also needs combine with other factors to study and quantify the SIV failure.
In this study, multi-level dual damascene Cu interconnects with the SIV testing structure, Kevlin structure, is applied to figure out factors to influence the SIV performance in the dual damascene process are also investigated. The SIV performance is presented by Cumulative Distribution Function (CDF) chart which is the common methodology in the semiconductor industry. SIV performance of this testing structure is improved and qualified after the process changes on the key steps in the dual damascene process loop such as electrochemical plating (ECP), metal thickness and alloy steps.
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