| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 100 === In recent years, embedded non-volatile memories are used in various systems. However, due to compatibility of processes, memory chips and the other functional chips are fabricated separately. If the memories can be integrated in the same chip with analog and digital circuits, the single chip is usually referred as SOC (system-on-a-chip). In the mean time, the cost and fabrication time can be reduced.
The thesis presents the design of the peripheral circuits for the CMOS-based non-volatile memory cells. The circuits perform program, erase, read and verify for the 8-bit memory array. These include the address decoder, word line driver, bit line driver, source line driver, current sense amplifier, verifying circuit and output stage. Specifically some of these circuits require high-voltage tolerant abilities owing to the operating voltages for program and erase higher than the standard voltage. The peripheral circuit was designed and fabricated. The measurement results show that the memory cells can be programmed and erased within 10 milliseconds and the time of reading for any address is within 11 nanoseconds.
Furthermore, the operation of the memory cells needs different bias voltages. Thus, the DC-DC step-down converter was designed. By comparison with low-dropout regulator (LDO), the DC-DC step-down converter employing the switched-capacitor structure can enhance the power efficiency for high voltage conversion ratio which is defined as Vout/Vin, such as 5 V to 1.8 V, 1.2 V and 1 V. The circuit was also designed and fabricated. The measurement results demonstrate the maximum load current is 44 mA with the peak efficiency of 68.6% for 1.8 V output. By switching to the 1.2 V and 1 V modes, the maximum load currents are 79 mA and 78 mA with the peak efficiencies of 67.9% and 54.8%, respectively.
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