Design of High Performance Binary Signed-Digit Adder

• Main Authors: Yu-Hau Tzeng, 曾于豪
• Other Authors: Shao-Hui Shieh
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/59050694178419002052

碩士 === 國立勤益科技大學 === 電子工程系 === 100 === Binary Signed-Digit (BSD) number representation has inherently carry-free (CF) addition. Hence, it is widely applied in design of parallel arithmetic and high performance processor. The structure of a BSD adder design is mainly composed of three blocks including binary-to-BSD conversion, BSD computing unit and BSD-to-binary conversion. In design of each block, we find that the binary-to-BSD conversion can be done in constant time. In addition, the performance of BSD-to-binary conversion almost dominates the whole performance of a BSD-based arithmetic system. In this thesis, a high performance BSD adder design is proposed to have the capability of on-line detection all single stuck-at fault and repairing in normal operation mode. The tree-structure two-rail code checker (TRC) is chosen in our self-checking and repair circuits design due to its simple and easier implementation. The BSD adder with self-repair capability can provides higher reliability. The validations and realizations of our design are based on TSMC 0.18μm process technology, and the experimental results have proved our design is valid and can effectively reduce the transistor count, carry propagation delay and power consumption.