An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD chips

• Main Authors: Jia-WenChang, 張嘉文
• Other Authors: Tsung-Yi Ho
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/36122081401816463694

碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === Electrowetting-on-dielectric (EWOD) chips have become the most popular actuators, particularly for droplet-based digital microfluidic (DMF) systems. In order to enable the electrical manipulations, wire routing is a key problem in designing EWOD chips. Unlike traditional very-large-scale-integration (VLSI) routing problems, in addition to routing-path establishment on signal pins, the pin-constrained EWOD-chip routing problem must address the issue of signal sharing for pin-count reduction under the practical constraint posed by a limited pin-count supply. Moreover, EWOD-chip designs might incur several obstacles in the routing region due to embedded devices for specific fluidic protocols. However, no existing work considers the EWOD-chip routing with obstacles and therefore lots of manual design efforts are involved. To remedy this insufficiency, we propose in this thesis the first routing algorithm for pin-constrained EWOD chips with obstacle avoidance. The proposed algorithm, based on effective integer-linear-programming (ILP) formulation as well as efficient routing framework, can achieve high routability with a low design complexity. Experimental results based on real-life chips with obstacles demonstrate the high routability of proposed routing algorithm for pin-constrained EWOD chips with obstacle avoidance.