A Non-Redundancy Decision Tree for Packet Classification
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === Packet Classification is one of the most important services provided by high speed Internet routers nowadays. To obtain the throughput of higher than 40Gbps (OC-768) , we need the hardware architecture support. If the entire data structure cannot be stored in...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2012
|
Online Access: | http://ndltd.ncl.edu.tw/handle/91858503723968058790 |
id |
ndltd-TW-100NCKU5392095 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-100NCKU53920952015-10-13T21:38:04Z http://ndltd.ncl.edu.tw/handle/91858503723968058790 A Non-Redundancy Decision Tree for Packet Classification 用於封包分類之無規則重複決策樹 Yu-HsiangWang 王煜翔 碩士 國立成功大學 資訊工程學系碩博士班 100 Packet Classification is one of the most important services provided by high speed Internet routers nowadays. To obtain the throughput of higher than 40Gbps (OC-768) , we need the hardware architecture support. If the entire data structure cannot be stored in on-chip memory of FPGA devices, the packet classification performance will be slowed down by external storage device. Decision tree based algorithms, such as HiCuts, HyperCuts and HyperSplit, have rule replication problem which might cause memory storage explosion. In this thesis, we propose a new scheme called CubeCuts that does not generate any rule replication. CubeCuts is a binary cutting scheme that constructs multiple decision trees. CubeCuts partitions the rule table by disjoint relationship and separates the search space by using the concept of hypercube. The address space of a node in CubeCuts decision tree is separated into the one inside the cut hypercube and the other one outside the cut hypercube. A heuristic to compute how to cut the hypercube is proposed. However, the skewed tree problem occurs in the Firewall and IPC tables of more than 15K rules. Therefore, a modified heuristic is also proposed to solve the skewed tree problem. Based on the proposed CubeCuts, we can have a memory-efficient data structure such that ACL table of 50K rules, Firewall table of 20K rules, and IPC table of 15K rules can be fit into the on-chip memory of FPGA. Our design is suitable to be implemented with parallel and pipeline architecture. The hardware implementation can achieve a throughput of 184 Gbps, which is enough to accommodate the Internet traffic that is growing rapidly in recent years. Yeim-Kuan Chang 張燕光 2012 學位論文 ; thesis 67 en_US |
collection |
NDLTD |
language |
en_US |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === Packet Classification is one of the most important services provided by high speed Internet routers nowadays. To obtain the throughput of higher than 40Gbps (OC-768) , we need the hardware architecture support. If the entire data structure cannot be stored in on-chip memory of FPGA devices, the packet classification performance will be slowed down by external storage device. Decision tree based algorithms, such as HiCuts, HyperCuts and HyperSplit, have rule replication problem which might cause memory storage explosion. In this thesis, we propose a new scheme called CubeCuts that does not generate any rule replication. CubeCuts is a binary cutting scheme that constructs multiple decision trees. CubeCuts partitions the rule table by disjoint relationship and separates the search space by using the concept of hypercube. The address space of a node in CubeCuts decision tree is separated into the one inside the cut hypercube and the other one outside the cut hypercube. A heuristic to compute how to cut the hypercube is proposed. However, the skewed tree problem occurs in the Firewall and IPC tables of more than 15K rules. Therefore, a modified heuristic is also proposed to solve the skewed tree problem. Based on the proposed CubeCuts, we can have a memory-efficient data structure such that ACL table of 50K rules, Firewall table of 20K rules, and IPC table of 15K rules can be fit into the on-chip memory of FPGA. Our design is suitable to be implemented with parallel and pipeline architecture. The hardware implementation can achieve a throughput of 184 Gbps, which is enough to accommodate the Internet traffic that is growing rapidly in recent years.
|
author2 |
Yeim-Kuan Chang |
author_facet |
Yeim-Kuan Chang Yu-HsiangWang 王煜翔 |
author |
Yu-HsiangWang 王煜翔 |
spellingShingle |
Yu-HsiangWang 王煜翔 A Non-Redundancy Decision Tree for Packet Classification |
author_sort |
Yu-HsiangWang |
title |
A Non-Redundancy Decision Tree for Packet Classification |
title_short |
A Non-Redundancy Decision Tree for Packet Classification |
title_full |
A Non-Redundancy Decision Tree for Packet Classification |
title_fullStr |
A Non-Redundancy Decision Tree for Packet Classification |
title_full_unstemmed |
A Non-Redundancy Decision Tree for Packet Classification |
title_sort |
non-redundancy decision tree for packet classification |
publishDate |
2012 |
url |
http://ndltd.ncl.edu.tw/handle/91858503723968058790 |
work_keys_str_mv |
AT yuhsiangwang anonredundancydecisiontreeforpacketclassification AT wángyùxiáng anonredundancydecisiontreeforpacketclassification AT yuhsiangwang yòngyúfēngbāofēnlèizhīwúguīzézhòngfùjuécèshù AT wángyùxiáng yòngyúfēngbāofēnlèizhīwúguīzézhòngfùjuécèshù AT yuhsiangwang nonredundancydecisiontreeforpacketclassification AT wángyùxiáng nonredundancydecisiontreeforpacketclassification |
_version_ |
1718067623250362368 |