| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === The complexity of modern IC design is increasing in a dramatic speed, which makes the number of pads in a chip grow exponentially. To enable a large amount of pads to connect to the boundaries of the pad matrix, the trend of using multiple layers to complete escape routing becomes necessary. Since cost and yields of a PCB are greatly impacted by layer number, developing an efficient and effective methodology to minimize routing layers becomes very important. However, most of designs in industry are still routed manually. It not only increases time-to-market but also consumes more routing layers. Therefore, we propose a new methodology to complete multi-layer escape routing for a large scale pad matrix. Since routing sequence of pads has a lot to do with required layer number, a novel cross patten is proposed to divide a pad matrix such that boundary channels in each layer can be increased. Besides, we propose an efficient and effective multi-direction search method to route each pad, which can avoid generating angle wires. The experimental results show that EDSM algorithm can be faster and no acute angle wires. With EDSM algorithm and cross pad division pattern, our routing methodology can achieve the same routing layers compared to Wang et. al. [18] in a very fast runtime. A 80 * 80 pad matrix can be routed by our algorithm in 4.84 sec.
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