A Statistic Approach to Synthesis High Variation-Tolerant Mesh for Constructing Low Power Clock Networks
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === Due to its high tolerance to process-variation, clock mesh is a widely used structure in a clock network for high performance synchronous VLSI designs. Since mesh structure induces more capacitance, the mesh based clock network usually consumes more power tha...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45859820660203496069 |