| Summary: | 碩士 === 國立成功大學 === 電機工程學系專班 === 100 === Though the system standards for the applications in the V-band of 57 to 64 GHz are still not clear, the main leadership design companies have already put a great effort on the integration of 60-GHz mm-wave front-end circuits. In this thesis, a 27-GHz voltage-controlled oscillator (VCO) with low power and low phase-noise performances are designed in a mature 0.18-um CMOS process. This oscillator can provide a 54-GHz signal in the case with the help of a frequency doubler.
From the measurement results measured by CIC, the output frequency of the VCO ranging from 26.96 to 27.95 GHz (with a tuning range of about 1 GHz). The total power consumption is 3.5 mW from a 1.8V supply voltage. The output power is -7.88 dBm. The measured phase noise at 27 GHz is -99.39 dBc/Hz @ 1MHz offset and -120.94 dBc/Hz@10 MHz offset. The calculated figure-of-merits (FOM) are about in the range of -182.56 dBc (at 1 MHz offset) and -184.11 dBc (at 10 MHz offset). The chip size is about 0.855x0.679 mm2.
It is shown that there are some inconsistences between the measurement and simulation results of phase noise. After EM simulation of inductor, it found the result is similar to measurement. In the future, for the more precise simulation results, the layout of inter connection lines, inductors, and capacitances have to be taken into the design. Simultaneously, we would like to transfer this design from a 0.18um CMOS to a 90nm CMOS process, in order to achieve the lower power and higher performance.
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