Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input dif...
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ndltd-TW-100NCKU54422392015-10-13T21:38:04Z http://ndltd.ncl.edu.tw/handle/24078815364182330693 Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications 應用於低耗電系統之連續漸進式類比數位轉換器 Ming-LunFan 范銘倫 碩士 國立成功大學 電機工程學系碩博士班 100 This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm. The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step. Chin-Lung Yang 楊慶隆 2012 學位論文 ; thesis 85 zh-TW |
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碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm.
The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step.
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author2 |
Chin-Lung Yang |
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Chin-Lung Yang Ming-LunFan 范銘倫 |
author |
Ming-LunFan 范銘倫 |
spellingShingle |
Ming-LunFan 范銘倫 Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
author_sort |
Ming-LunFan |
title |
Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
title_short |
Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
title_full |
Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
title_fullStr |
Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
title_full_unstemmed |
Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications |
title_sort |
successive-approximation analog-to-digital converter for low-power system applications |
publishDate |
2012 |
url |
http://ndltd.ncl.edu.tw/handle/24078815364182330693 |
work_keys_str_mv |
AT minglunfan successiveapproximationanalogtodigitalconverterforlowpowersystemapplications AT fànmínglún successiveapproximationanalogtodigitalconverterforlowpowersystemapplications AT minglunfan yīngyòngyúdīhàodiànxìtǒngzhīliánxùjiànjìnshìlèibǐshùwèizhuǎnhuànqì AT fànmínglún yīngyòngyúdīhàodiànxìtǒngzhīliánxùjiànjìnshìlèibǐshùwèizhuǎnhuànqì |
_version_ |
1718067703621615616 |