Architecture-Aware Instruction-Based Power Model Considering Voltage and Frequency Scaling For ESL Virtual Platforms
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === Power consumption of digital electronic has become one of the important issues in recent years. Voltage and frequency of a module can be configured dynamically to reduce power consumption of hardware. Each block can be avoided simultaneously activating to con...
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| Format: | Others |
| Language: | en_US |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87950567573881406080 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === Power consumption of digital electronic has become one of the important issues in recent years. Voltage and frequency of a module can be configured dynamically to reduce power consumption of hardware. Each block can be avoided simultaneously activating to consume power by using task scheduling of the software. Therefore, an electronic-system level virtual platform integrated with power models to perform fast software and hardware co-simulation is needed. It can help designers developing power management algorithms to dynamically adjust the operating voltage and frequency of the system.
In this work, we have developed power models for a general-purpose processor, memories and a subsystem. Experimental results show that the high-level processor power model can be confined within 5% of errors of the power obtained by PrimeTime.
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