Trace Reuse Cache for RISC Processor Architecture

• Main Authors: Hang-ChinKuo, 郭漢衿
• Other Authors: Chung-Ho Chen
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/47497086044950085121

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 100 === In this thesis, we propose a new mechanism named Trace Reuse Cache (TRC) for instructions delivery to reduce power consumption of RISC processor architecture. With additional circuit in CPU fetch stage and TRC, it is possible to choose suitable instructions in the system for reuse, and to get better performance. We also analyze the whole system and evaluate the IPC, hit rate, and power consumption. Based on an ARM-compatible 5-stage RISC core, we attach the TRC to the cache memory system and modify part of the pipeline architecture for supporting TRC instruction delivery with small area overhead. The purpose is to lower the power consumption of cache itself and benefit the instruction fetching performance. Experimental result shows that there is less power dissipation in our work than traditional case only with an instruction cache. Moreover, TRC provides the designer with an additional option, and has possibility to enhance system.