Trace Reuse Cache for RISC Processor Architecture
碩士 === 國立成功大學 === 電腦與通信工程研究所 === 100 === In this thesis, we propose a new mechanism named Trace Reuse Cache (TRC) for instructions delivery to reduce power consumption of RISC processor architecture. With additional circuit in CPU fetch stage and TRC, it is possible to choose suitable instructions...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47497086044950085121 |