Design and Implementation of Reconfigurable Memory for LTE Modem

• Main Authors: Weng, Chen-Che, 翁晨哲
• Other Authors: 許騰尹
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/87599794173313472488

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === This thesis is proposed to the shared memory pool as based architecture of LTE modem. This architecture is combined of two computing units such as Fast Fourier Transform (FFT) and Arithmetic Logical Unit (ALU); five algorithms such as Cell Search, Carrier Frequency Offset (CFO), Sampling Clock Offset (SCO), Channel Estimation. Architecture of the LTE modem is implemented by hardware description language as Verilog, all circuits are implemented by standard-cell-based design. This architecture of modem can change or add algorithm by modifying the shared memory pool to reduce design cost.