Design and Implementation of a Low Memory Access Network Intrusion Detection System with a Small on-Chip Memory
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === In this work, a low memory access network intrusion detection system (NIDS) with a small on-chip memory is presented. The proposed NIDS employs three techniques: 1) page segmentation scheme in off-chip memory, 2) 2-way set associate pattern information page (...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/35522193729035197638 |
| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === In this work, a low memory access network intrusion detection system (NIDS) with a small on-chip memory is presented. The proposed NIDS employs three techniques: 1) page segmentation scheme in off-chip memory, 2) 2-way set associate pattern information page (PIP) cache, 3) packet pre-filter scheme. By adopting the three techniques, the system can reduce the number of memory accesses and is able to integrate with Ethernet media access controller (MAC). From the implementation result, the proposed NIDS can perform up to 2Gbps intrusion detection speed with only 4.04KB on-chip memory and support up to 4GB memory space in 32-bit system.
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