Design of Dual-Core Java Application Processor for Embedded Systems

• Main Authors: Guo, Zi-Jing, 郭子敬
• Other Authors: Tsai, Chun-Jen
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/14424246338156296385

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 100 === This thesis presents the design of the exception handling architecture of a Java processor. Although there are many research publications on Java processor designs, there is no efficient implementation on Java exception handling circuitry. Most Java processor design papers simply ignore exception handling while some claims that a hardwired implementation of exception handling conforming to the Java language specification is quite complex to implement. In this thesis, we have proposed an efficient design of the Java exception handling mechanism and the associated two-level method area. We have also integrated the design into a heterogeneous dual-core Java processor. With the proposed two-level method area, the exception handling overheads are delayed to the time after an exception actually occurs. More importantly, the process of exception handling is mostly performed in the Java core with very little runtime overhead from the RISC core. As a result, the proposed design reduces the amount of inter-processor communication and circuit design cost of the Java core while enabling full support of Java exception handling. We have implemented the design on a Xilinx ML-507 FPGA platform. As the experiments show, the proposed design is very promising for embedded applications.