Advanced Modeling of Gate Tunneling Current in CMOSFETs and FinFETs and Its Potential Application

• Main Authors: Hsu, Chih-Yu, 許智育
• Other Authors: Chen, Ming-Jer
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/16154671587461601128

博士 === 國立交通大學 === 電子研究所 === 100 === Analytic gate direct tunneling and Fowler-Nordheim tunneling current model for conventional polysilicon gate oxide MOSFETs and present-day metal-gate/high-k/IL gate stack CMOSFETs and n-FinFETs is established. In addition, trap related tunneling is incorporated as well. Validity of the model, with the known effective masses and subband energies created using an in-house quantum confinement simulator, is thoroughly corroborated. Particularly, advanced techniques on the application of the model are proposed for the first time. Resulting process and material parameters of the device under study not only can provide new insight into underlying manufacturing process but also can be quantitatively more accurate than those obtained from conventional method without advanced techniques in this work. At first, on a nominally 1.27-nm thick gate oxide p-MOSFET with STI longitudinal compressive mechanical stress, experimental hole gate tunneling current exhibits an increasing trend with STI compressive stress. However, this is exactly opposed to the currently recognized trend: Hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain altered valence-band splitting. To determine the mechanisms responsible, the combination of the model and a quantum strain simulator is established and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: A reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain altered valence-band splitting. Next, for planar bulk n-MOSFET low-EOT (1.4 nm) TaC/HfSiON/SiON high-k gate stacks, there is a transition region in the electron gate tunneling current Ig, as characterized by a plot of dlnIg/dVg versus Vg. Here, we systematically construct a new fitting over the region, which can accurately determine the material parameters including the metal workfunction, the high-k electron affinity, and the tunneling effective masses of electrons. First of all, a calculation of gate current due to electron direct tunneling and/or Fowler-Nordheim tunneling from the inversion layer is performed, yielding the guidelines of the fitting. The underlying material parameters are extracted accordingly and remain valid for higher temperature and gate voltage. We also demonstrate that the conventional method without the dlnIg/dVg fitting might lead to erroneous results. Thus, dlnIg/dVg fitting is crucial to the metal-gate high-k material parameters assessment. In addition to electron tunneling from inversion layer to metal electrode, additional tunneling component via the interface states is shown to be significant in reproducing experimental gate leakage current. Further, for 0.75-nm EOT TiN/HfO2/SiON nMOSFETs, experimental gate tunneling current and its dlIg/dVg fittings are presented. First of all, electron tunneling effective mass in HfO2 dielectric lies at around 0.03 mo, which is consistent with the HfSiON counterpart. This dictates some unexplained physical mechanisms, which not only are common to both HfO2 and HfSiON but also are responsible for unconventionally low effective mass in tunneling. Furthermore, a graded transition (intermixing) region from SiON interfacial layer to HfO2 high-? can ensure a good fitting. This suggests that a transition layer exists in HfO2 based high-k gate stacks whereas it does not exist in HfSiON/SiON gate stacks. The importance of electron tunneling via IL/Si interface states in overall gate leakage is highlighted. For both 1.5 nm-EOT TaC/HfSiON/SiON and 0.85nm-EOT TiN/HfO2/SiON gate dielectric p-MOSFET counterparts, a comprehensive fitting of measured tunneling current components through source/drain, bulk, and gate is performed. Combining electron direct and F-N tunneling from both the inversion layer and IL/Si interface states with the trap-assisted tunneling (TAT) current around the favorable trap (in interfacial layer for the maximum tunneling probability there), the experimental hole tunneling current for TiN/HfO2/SiON gate dielectric pMOSFETs is reproduced well. However, TAT mechanism does not exist in the experimental gate current data for TaC/HfSiON/SiON gate stacks pMOSFETs. The fittings of the substrate current stemming from gate-to-substrate electron tunneling for both test devices are also conducted. Furthermore, the importance of extra dlnIg/dVg-Vg fitting to ensure accurate assessment of gate material parameters is highlighted as well. At this point, we will demonstrate advanced modeling in 0.8-nm EOT HfO2 based high-k/metal-gate n-FinFETs. First of all, an analytic model suitable for double-gate structure is newly constructed. Then, the combination of Ig-Vg, Cg-Vg, and additional dlnIg/dVg-Vg curve fittings leads to several remarkable results. First, only with a transition layer between high-k and interfacial layer can a good fitting be obtained, as supported by TEM analysis. Second, the tunneling effective mass in HfO2 based high-k dielectric is around 0.02 m0, a minimum value reported to date. Third, all extracted gate material parameters remain valid, taking into account the difference between (001) and (110) surfaces, for the planar bulk n-MOSFET counterparts formed on the same wafer. Finally, the experimental electron tunneling current at low gate bias can be fitted well by adding the role of tunneling from IL/Si interface states to metal gate.