Subthreshold SRAM Design and Implementation for Ultra-Low Power Dissipation
博士 === 國立交通大學 === 電子研究所 === 100 === Recently, the demand for ultra-low power dissipation battery-operated devices is increasing. When the performance at low supply voltage (VDD) meets system requirement, scaling down the supply voltage reduces power dissipation significantly. A circuit can achieve u...
Main Authors: | Tu, Ming-Hsien, 杜明賢 |
---|---|
Other Authors: | Jou, Shyh-Jye |
Format: | Others |
Language: | en_US |
Published: |
2011
|
Online Access: | http://ndltd.ncl.edu.tw/handle/80438418998483471522 |
Similar Items
-
Robust Subthreshold SRAM and Ultra-Low Power FIFO Memory Design
by: Mu-Tien Chang, et al.
Published: (2008) -
Subthreshold Operation and Low-Power Embedded SRAM Design and Implementation
by: Chiu, Yi-Wei, et al.
Published: (2014) -
An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications
by: Arijit Banerjee, et al.
Published: (2014-05-01) -
Testing open defects for subthreshold SRAM designs
by: Chen, Hung-Hsin, et al.
Published: (2010) -
SNM-Aware Subthreshold SRAM Cell and Array Designs
by: WENG, WEI-JIA, et al.
Published: (2017)