| Summary: | 博士 === 國立交通大學 === 電子研究所 === 100 === In wireless communication, the data-rate requirement is significantly increasing from the text/file delivery until the real-time image communication. The frequency is rapidly moving to the high frequency for demand of high-data rate. For high-date rate requirement, the standard of short-distance data communication is presented, such as 60-GHz system (IEEE 802.15) and W-band system, in place of 2.4-GHz system (IEEE 802.11 a/b/g/n) and concurrent system of 2.4-GHz and 5-GHz frequency. In the vehicle radar system, the operation frequency is also push up to 77 GHz. Traditionally, these high frequency systems are realized by expensive process, like, GaAs..., because of high performance of the device in these expensive process. Thus these circuits are very difficult to be popularized. Fortunately, the performance of popular CMOS process is also rapidly improving. In advance CMOS process, the cut-off frequency is reaching up than 100 GHz. Recently, the CMOS high frequency circuits are gradually realized in order to decrease the cost. However, some of these circuits is very power hungry for operating in high frequency operation. In this thesis, we design several receivers with rather low power consumption for recent proposed high frequency application. In these receivers, the circuits are including low noise amplifier, mixer, voltage control oscillator, balun and IF amplifier.
At first, a new structure to implement the low noise amplifier suitable for high frequency operation. In this technique, the enlarger cut-off frequency of FET and good-isolation can be reached. Thus the gain of low noise amplifier can be boosted. A CMOS 24-GHz low noise amplifier for vehicle radar application has been designed and fabricated in CMOS 0.18-?慆 process with a chip area of 0.77 x 0.84 ?慆2. From the measurement results, this amplifier has gain of 10.1 dB, noise figure of 3.8 dB and the power consumption of 14 mW from 1-V supply voltage.
Secondly, a CMOS 77-GHz front-end receiver for vehicle radar application is presented in this thesis. This front-end receiver is consisted of a two-stage low noise amplifier, a second-order sub-harmonic mixer, a voltage control oscillator, a balun and a intermediate frequency amplifier. The proposed structure of low noise amplifier is redesign in 77 GHz. In order to decrease the integrating difficulties and the power consumption, the traditional mixer is replaced by the second-order sub-harmonic mixer. Besides, a single-end radio frequency output signal of low noise amplifier is transformed to two differential-end signals in order to fed into the second-order sub-harmonic mixer through the balun. This receiver has been designed and fabricated in CMOS 0.13-?慆 process with a chip area of 1150×1050 ?慆2. From the measurement results, with intermediate frequency of 200 MHz, this receiver has a gain of 21.8 dB. By increasing the intermediate frequency to 1 GHz, this receiver has a gain of 11.8 dB with a noise figure of 14.5. The power consumption is 13.5 mW from the 1-V supply voltage.
A 51.6-55-GHz CMOS receiver front-end designed with new third-order sub-harmonic mixer and on-chip wide-tuning-range VCO is proposed, analyzed, and fabricated for millimeter-wave (MMW) UWB applications. The proposed receiver consists of a broadband-matching LNA, active sub-harmonic mixers, a quadrature VCO, IF amplifiers, and output buffers. The use of third-order sub-harmonic mixer has advantages of low LO leakage to RF ports, low DC offset, and low gain/phase mismatch. Moreover, the wide-tuning-range quadrature VCO integrated on the same chip to cover the full UWB bandwidth and decrease power dissipation. The proposed receiver is fabricated in 130-nm CMOS technology with a chip area of 1385 ?慆 × 1070 ?慆 and low power consumption of 32.38 mW. In addition, the integrated VCO provides a wide tuning range from 17.2 GHz to 21.4 GHz (21.7%). The simulated LO leakage to RF posts is below -40 dB. Within the 3-dB bandwidth of 51.6 to 55 GHz, the gain of receive is maintained above 21 dB and noise figure is below 18.1 dB.
Finally, a CMOS 78~102 GHz front-end receiver is presented in this thesis. The demand for high frequency and ultra-wide band has larger challenges not only in the circuits but also in the architecture. The proposed receiver is consisted of a broadband low noise amplifier, a second-order sub-harmonic mixer with a intermediate frequency amplifier. In order to suffice for the requirement of ultra-wide band, the three stage low noise amplifiers have been integrated in this receiver. The frequency of maximum gain in each stage is made an arrangement in differential frequency for extending the bandwidth of low noise amplifier. Within the bandwidth, the highest peak-gain frequency stage is in the first to boost the gain of highest frequency, and the lowest is in the last stage to reduce the difficulties in the integration. In order to decrease the integrating difficulties and the power consumption, the traditional mixer is replaced by the second-order sub-harmonic mixer. This receiver has been designed and fabricated in CMOS 90-nm process with a chip area of 680×1020 ?慆2. From the measurement results, this receiver has a power consumption of 18.6 mW from 1.2-V supply voltage, a ultra-wide 3-dB bandwidth of 78-102 GHz. When the intermediate frequency is at 1 GHz, the receiver has a maximum gain of 11.8 dB with a noise figure of 13.4 under the radio frequency is at 94 GHz.
In this thesis, the several high frequency receivers have been designed and fabricated in CMOS process. In order to enhance the performance and reduce the power consumption, a new low noise amplifier has been proposed in this thesis, and sequentially designed in 24-GHz, 77-GHz, 51.6-55-GHz and 78~102-GHz systems. Besides, the high frequency, low power dissipation and high integration are achieved in proposed receivers of this thesis. In the future, these receivers can be optimized for the variation of corner and temperature and integrated with baseband circuits to become a more complete system.
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