| Summary: | 碩士 === 國立交通大學 === 電機學院電信學程 === 100 === This thesis discusses the design and analysis of an ultra wideband low noise amplifier. It has the advantage of high gain, high linearity, low noise, low power consumption and small chip size. The ultra wideband low noise amplifier was implemented in TSMC 0.18 um CMOS technology and based on the cascode resistive feedback architecture with bandwidth extension by series peaking inductor. The first part introduces series LC band pass filter to achieve input matching. The second part introduces resistive feedback with series inductive peaking configuration to extend bandwidth and gain. The measured bandwidth of the low noise amplifier covers UWB 3.1-10.6GHz and within this band the gain is 8 ~12.5 dB, the noise figure is 2.9 ~ 4.3 dB, the input return loss is below -10.0 dB, the output return loss is below -10.0 dB. The input third intercept point(IIP3) measured at 6.8GHz is +5.0 dBm, the input power at 1dB gain compression point(P1dB) at 6.8GHz is -5.5 dBm. This low noise amplifier consumes 18 mW from a 1.5 V power supply. The chip size included pad is
0.68 mm2.
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