3.1-10.6 GHz Ultra-Wideband Low-Power Self-Body-Bias Low-Noise Amplifier

• Main Authors: Huang, Chih-Wei, 黃至偉
• Other Authors: Tarng, Jenn-Hwan
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/03558202011690930868

碩士 === 國立交通大學 === 電信工程研究所 === 100 === In this thesis, the research focuses on how to reduce the power consumption and noise figure. In general, the substrate bias produce a sufficient voltage drop using resistor feedback to enhance the potential of the substrate side, decreasing the over drive voltage (Vt) of the transistor can reduce the supply voltage . Usually, it could use resistive body bias but noise was easy leak from the base end result in higher noise figure. The design of the circuit architecture improved the basic framework , we use transistor body bias to replace the traditional architecture of the resistor body bias, because the noise figure of the amplifier come from the size of the transistor. It is different from the resistance, the transistor is a nonlinear element, so we only need to select the small size of transistors, and then generate enough voltage drop in the drain - source end. It is an effective noise suppression. Because the parasitic effect of the transistors makes the frequency response of the pole move to the low frequency band. In order to improve the problem, we adopt the CG the CG cascode architecture in the input stage and join the center-tapped inductor as gain compensation. The center tap inductor can control the voltage of the self body bias, and it can also save an additional bias circuit, so that the substrate bias transistor and the drain inductance form the Gm-boosted architecture to increase its high-frequency response and the S12 isolation. The measured results are as follows: bandwidth of 3.1 ~ 10.6 GHz, input and output reflection loss are greater than -10 dB, the maximum power gain is 14 dB, the minimum noise figure is 3.2 dB, at 3.1 GHz and 6 GHz, the P1dB gain compression point is -13 dBm and -12 dBm, the IIP3 cut-off point is -2 dBm and -3 dBm, the core circuit power consumption is 8.95 mW, and the overall layout area including the pads is 0.84 * 0.89 = 0.75 mm2.