Vertical Signal Transmission in Three-Dimensional Integrated Circuits by Common-Resistive Layer
碩士 === 國立交通大學 === 電控工程研究所 === 100 === This thesis proposes a die-to-die communication mechanism. Its transmitting medium is a common-resistive layer. In the transmitter design, to boost the operating speed and reduce leakage power originated from the neighboring pads, a dual-NMOS driver is used. In...
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| Format: | Others |
| Language: | en_US |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41855846040412529254 |