Triple Loop Modulation (TLM) for High Reliability and Efficiency in Power Factor Correction (PFC) System

• Main Authors: Chen, Chi-Lin, 陳契霖
• Other Authors: Chen, Ke-Horng
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/85164771988645998761

博士 === 國立交通大學 === 電控工程研究所 === 100 === In general power applications, the power factor correction techniques is the one of key techniques in power saving applications and can make AC power more efficient. The PFC has slow system response because it has low one third or one sixth bandwidth smaller than 20 Hz. The low bandwidth is designed to reject AC interference of 60Hz coupling which could deteriorate system reliability in case of output load transient. This dissertation proposes the triple loop modulation (TLM) in PFC system to improve as fast transient response. When system is in steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. When output loading changes, the TLM can automatically adjust the bandwidth to increase or decrease inductor current rapidly and reduce transient response time. The mathematical analysis is deduced. This PFC chip is fabricated in VIS 0.5um 500V/40V ultra high voltage LDMOS process. Measurement results show that this PFC system with TLM in transient response is twofold faster than conventional PFC design with output load variation from 20W to 90W and the undershoot voltage is half of traditional PFC. When loading changes from 20W to 90W, the PFC with TLM in transient response is twofold faster than conventional PFC design and the overshoot voltage is about half of traditional PFC.