Ground Bounce Analysis of High Speed PCB and Power Integrity Design and Simulation

• Main Authors: Huang, Shih-Hang, 黃士航
• Other Authors: Tzou, Ying-Yu
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/20363556360513227723

碩士 === 國立交通大學 === 電機學院電機與控制學程 === 100 === In recent year, climbing frequency and descending supply voltage of digital circuit that cause power delivery network (PDN) design become more difficult. In this thesis, we discuss the effect of the ground bounce noise (GBN) and how it affects the power integrity (PI). At first, we introduce the phenomenon of the GBN and refer working pattern of CPU to analysis the impedance requirement. We try to define the target impedances of the low and high frequency of the PDN, and compare the distributions of the impedance that measured by network analyzer to one simulated by SIwave in frequency domain. Time domain simulation is also achieved by ADS circuit simulator to verify if the result is expected. Adding de-coupling capacitors is a typical way to suppress the GBN. We analyze the de-coupling characteristic of capacitors to find the appropriate component and the loop inductance of the PDN based on PCB stack-up. It helps us to find a design rule to decrease the loop inductance and the GBN on the power rail. Finally, we set up a method to design the de-coupling radius for the PDN to find out the placed range of the de-coupling capacitors.