Design of All Digital Phase-Locked Loop and Application in Built-in Jitter Measurement
博士 === 國立中央大學 === 電機工程研究所 === 100 === With green energy-saving clocking systems, the high speed and low power consumption phase-locked loop (PLL) and delay-locked loop (DLL) are popular to solve the clock skew. The low jitter and high frequency accuracy of clock sources can improve the reliability...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01527510041182865954 |