| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 100 === The title of this thesis is “The Design and Implementation of Wideband CMOS Low Noise Amplifier for UWB and V-Band Applications”, in this thesis, we study the design of wideband and low power realization used in low noise amplifier and finally, we bring up four different circuit with wideband technique.
The first circuit is “A Low-Power Wideband Self-Biased Low Noise Amplifier
for UWB Receiver Front-End”, the emphasis of this circuit is how to boost gain、bandwidth and reduce power consumption, and the way is that we can boost the normal bandwidth effectively by the way of MOSFET and resistor feedback, the purpose of inductive-peaking is series resonate with parasitic capacitor and by this way, the gain-boosting and noise reduction can be realization. Because of the low gain of feedback, the Gm- enhancement CASCODE is used and the reason is that we can acquire the higher transconductance by the current-reuse topology. Through the connection of current-mirror at the input and output stage, the bias of this circuit is total self-biased, by the condition of bias at output, the lowest power consumption of this circuit can be taken via this consideration. This LNA achieved a measured gain of 13.9 dB from DC to 4.8 GHz. The input and output return is 20.2 dB and 17.5 dB, respectively. The measured NF is 2.78 dB and IIP3 is -14dBm. The power consumption is totally 10.45 mW. The chip area is 0.462 mm2. Finally, this circuit is processed by tsmc^TM 0.18 μm CMOS process.
The second circuit is“A Low-Power Wideband Self-Biased Low Noise Amplifier
For 3.1-10.6 GHz application”, the emphasis of this circuit is how to boost gain、bandwidth and reduce power consumption in 3.1-10.6 GHz, and the way is that we use resistor feedback to realize normal bandwidth, because of the miller effect, we add a inductor at Drain in order to resonate parasitic capacitor, therefore, we can get the bandwidth about 12 GHz. The final stage is a common-source topology. PMOS as a active load is used, then, the properties of bias is self-biased. This LNA achieved a measured gain of 13.9 dB from 2 to 13 GHz. The input and output return is 14 dB and 19 dB, respectively. The measured NF is 3.6 dB and IIP3 is -4.8dBm. The power consumption is totally 11 mW. The chip area is 0.574 mm2. Finally, this circuit is processed by tsmc^TM 0.18 μm CMOS process.
The third circuit is “A Wideband V-Band Low Nosie Amplifier”, the emphasis of this circuit is to boost gain、bandwidth, and the way is that we realize wideband input and output matching, in a sigle common-source architecture, all the matching network including inter-stage is low Q type, bandwidth can be boosted effectively through this way. Next, through the CASCADE of 3-stages CASODE, the properties of wideband is achieved in application. In the limit of high noise of MOSFET at V-Band, we add a inductor in CASCODE, therefore, the noise generated from gate can be limited. This LNA achieved a measured gain of 10.9 dB from 50 to 59 GHz. The input and output return is 17.9 dB and 9.8 dB, respectively. The measured NF is 6.4 dB and IIP3 is +0.7 dBm. The power consumption is totally 35 mW. The chip area is 0.706 mm2. Finally, this circuit is processed by tsmc^TM 90 μm CMOS process.
The fourth circuit is “A V-Band Wideband Low Power Low Nosie Amplifier” the emphasis of this circuit is how to boost bandwidth and reduce power consumption, and the way is that we set up the power consumption, and then calculate the maximum current flow though a single common-source, under the selected size, we can get the best performance of MAG and NFmin. This LNA achieved a measured gain of 11.8 dB from 45 to 57 GHz. The input and output return is 14 dB and 23 dB, respectively. The measured NF is 5.7 dB and IIP3 is -9.5 dBm. The power consumption is totally 13.5 mW. The chip area is 0.525 mm2. Finally, this circuit is processed by tsmc^TM 90 μm CMOS process.
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