| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 100 === The output power and power added efficiency of power amplifiers implemented in standard CMOS are limited due to silicon substrate loss and low quality factor of passive components. This thesis presented CMOS power amplifiers with the matching networks fabricated by glass substrate integrated passive device (GIPD) process. By using GIPD process, it is possible to obtain the improved quality factor of passive components and reduced substrate loss.
First of all, a cascode device model based on TSMC CMOS 0.18 μm RF NMOS with parasitic effect was proposed and investigated with validation of dc, ac, and power characteristics. The cascode arrangement of transistors was used to increase operation voltage and thus higher output power capability. Subsequently, two CMOS power amplifiers using proposed cascode device model and GIPD process were designed and characterized. Class-E and class-AB power amplifiers were studied with single-end input and output but differential operation inside. In the class-E amplifier, the driver stage was implemented by mode-locking methodology and power stage was implemented in cascode. In the class-AB amplifier, transistors in both stages were connected in cascode for maximum output power. The measured power performance was not as good as simulated, the possible cause was from the flip-chip bumps.
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