| Summary: | 碩士 === 國立彰化師範大學 === 資訊工程學系 === 100 === Embedded system and wireless system are rapid growth from fixed device to mobile device that about financial, commercial, and Internet-based operation request. Binary number can’t express decimal number a precise value that and low-power become important problems. In this paper, we present a design that is used an abacus architecture for decimal adder. In operation speed, abacus decimal adder appears it is better. In power consumption, abacus adder also has been a prominent result. In this research, the design of abacus decimal adder has been simulated with HSPICE using the transistor models of PTM and TSMC 0.18um 1P6M CMOS technology, respectively. For the pre-simulation, in TSMC 0.18um 1P6M CMOS technology one of the power consumption is 7.38uW, maximum delay time is 479.952ps at 100MHz. For the post-simulation, in TSMC 0.18um 1P6M CMOS technology one of the power consumption is 25.674uW, maximum delay time is 1211.9ps, chip area is 1720um2. In this paper, the proposed decimal adder design is 22% faster than the fastest known decimal adder.
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