A Study of Delay-Locked Loop based Frequency Multiplier

A Study of Delay-Locked Loop based Frequency Multiplier

碩士 === 國立彰化師範大學 === 電子工程學系 === 100 === In this thesis, a frequency multiplier is studied, which consists of the delay-locked loop with pre-charged circuit and frequency multiplying circuits. The output frequency varies from 0.5 to 4 times of input frequency, step-up by 0.5. So totally, there are eig...

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Bibliographic Details
Main Authors:	Ying-Chieh Chen, 陳穎傑
Other Authors:	Hsun-Hsiang Chen
Format:	Others
Language:	zh-TW
Published:	2012
Online Access:	http://ndltd.ncl.edu.tw/handle/28375054858861740368

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