| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 100 === This thesis proposes a novel 0.9V 10-bit Successive Approximation (SAR) analog-to-digital converter (ADC) based on half junction splitting (J.S.) and half binary weighted capacitor digital-to-analog converter (DAC) architecture. The kick-back noise of this structure due to comparator is larger than other DAC structures, thus a modified rail-to-rail comparator is used to reduce kick-back noise. This ADC is implemented in sub-threshold to reduce power consumption. In addition, dummy comparators are used in different sections of DAC to reduce the offset voltage caused by different gain errors of different DAC sections. The pre-simulation shows that the power dissipation is 1.27μW, SNDR is 61.7dB, ENOB is 9.96-bit, and figure-of-merit (FOM) is 12.8 fJ/conversion step.
The chip has been fabricated with TMSC 0.18μm 1P6M CMOS process. The chip area is 893�e893μm2 with pads, and the core area is 440�e430μm2. The post-layout simulation shows that the power consumption is 1.72μW, the SNDR is 59.1dB, ENOB is 9.53-bit, and FOM is 23.2 fJ/conversion step.
Under 0.9V supply voltage and 100KS/s sampling rate, the measurement result shows that the power dissipation was 1.59μW, SNDR was 46.47dB, ENOB was 7.43-bit, and FOM was 92.2 fJ/conversion step. This chip worked under 0.6 V supply voltage and consumed only 0.783μW. This low-power ADC is suitable for bio-medical signal acquisition.
This low-power ADC is suitable for bio-medical signal acquisition.
|
|---|
