| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === In recent years, applications of wireless communication have been growing rapidly. Meanwhile, more specifications of wireless communication have been developed, so different receivers are needed. Therefore, it is desirable to combine these systems into one receiver. Software-Defined Radio, SDR [1], is one of these techniques to realize a multi-standard receiver by processing signal in the software. By this method, resources such as analog RF frontends and analog-to-digital converters (ADCs) can be shared between different modulations. To do so, an ADC that is able to adjust its resolution and conversion rate is necessary.
The pipelined ADC has been widely utilized in mid-resolution, high-speed applications. In this thesis, a switched-capacitor technique and a power reconfigurable opamp are proposed, which allow the system to optimize its power consumption with system bandwidth and resolution. Output codes of the designed ADC exhibit a SNDR of 48.6 dB. Fabricated in the 90nm CMOS technology, the core of the reconfigurable pipelined ADC occupies 0.27mm2. The opamp-sharing and capacitor-sharing techniques reduce the core power consumption to 32mW from a 1V supply voltage at 200MS/s. By the reconfiguration, the power consumption can be reduced to 18.5mW and 13mW at the conversion rate of 100MS/s and 50MS/s, respectively. At the end of this thesis, an analysis is performed to compare pipelined architectures with fast-growing SAR ADCs. This analysis helps the direction of future development.
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