| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === In recent years, the speed of chip-to-chip communication is upgrading which makes the speed of whole system to be faster. Hence, under high speed system, its noise coupling would not be ignored. This paper will propose a series of discussion for the signal integrity and power integrity of I/O interface circuits. This thesis presents two I/O transmission interface circuits which are voltage mode OCD (VMOCD) and current mode OCD (CMOCD). They are all operated at 1.1V, 3.2Gbps data rates and produced by standard UMC 90-nm CMOS process. And the transmitter and receiver circuits are included in the chip. To discuss the signal integrity and power integrity issues, many decoupling capacitors and extra transmitter circuits are added then observed the eye-diagram variation in each kind of different case.
In this thesis, discussion about two I/O interface circuits, and the simulation and measurement each other, then compare their results. The current mode OCD (CMOCD) has more noise resistance than the voltage mode OCD (VMOCD). And its power consumption is also lower. According to the difference between simulation and real test board measurement, the importance of model establishment for package and test board under high speed circuit are known. Therefore, the model establishment is added into the simulation. Finally, the results of the simulation and measurement are presented.
|
|---|
