| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 100 === In this thesis, two different kinds of transceivers for optical communication have been proposed, including a front-end circuit used in laser ranging radar and a 2×25-Gb/s
serializer/desrializer (SERDES) for 100-Gb/s Ethernet. They are both implemented in 65-nm CMOS technology.
In laser ranging radar, the front-end circuit adopts two-threshold method to eliminate walk error of the radar, and uses a calibration circuit to correct the voltage offset . The front-end circuit, optical component, and time-to-digital converter (TDC)can be integrated to a complete ranging radar, and the radar utilizes a modulated clock algorithm to improve accuracy. Finally, it achieves a accuracy of less than 3 mm and consumes 50 mW.
In 2×25-Gb/s SERDES, 2^7-1 pseudo random binary sequence (PRBS) generator, multiplexer (MUX), and feed-forward equalizer (FFE) are implemented in serializer.
The deserializer includes limiting amplifier, clock and data recovery (CDR) circuit, and demultiplexer (DMUX). Furthermore, serializer and desrializer have their respective clock generators. The chip-set can achieves BER < 10^-12, and consumes 300 mW and 520 mW in serializer and deserilizer, respectively.
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