The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits

碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === This thesis presents the design and realization of Si-based and SiGe-based optical receiving and light emitting integrated circuits, including limiting amplifier, burst-mode automatic gain controlled (AGC) transimpedance amplifier and light receiving and emittin...

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Main Authors: Po-hung Lin, 林柏宏
Other Authors: Shih-hsiang Hsu
Format: Others
Language:zh-TW
Published: 2012
Online Access:http://ndltd.ncl.edu.tw/handle/98141978414241815376
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spelling ndltd-TW-100NTUS54281292015-10-13T21:17:26Z http://ndltd.ncl.edu.tw/handle/98141978414241815376 The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits 矽基與矽鍺基光通訊與光互連積體電路設計及實現 Po-hung Lin 林柏宏 碩士 國立臺灣科技大學 電子工程系 100 This thesis presents the design and realization of Si-based and SiGe-based optical receiving and light emitting integrated circuits, including limiting amplifier, burst-mode automatic gain controlled (AGC) transimpedance amplifier and light receiving and emitting device. First, the designs of transimpedance and limiting amplifier using the TSMC 0.18μm CMOS 1P6M process are made. The RGC-type input stage is used in the circuits. It effectively isolate input parasitic capacitance, and therefore increases bandwidth performance. By adding limiting amplifier, the output swing is raised and restricts output voltage to the logic level. At 1.8V and 0.25pF input capacitance to our design, the simulated bandwidth is 3.7GHz for a gain of 73.9dBΩ and a total power consumption of 58.2mW. Secondly, we present a design of a burst-mode receiving circuit using RGC-type TIA with AGC circuit and variable gain amplifier (VGA). We use the TSMC 0.18μm SiGe BiCMOS process. At 1.8V and 0.25pF input capacitance to our design, the simulated dynamic gain range, the corresponding dynamic bandwidth range, and the total power consumption are 58.6~77.2dBΩ, 2.5~3.6GHz, and 84.9mW respectively. Finally, we use the TSMC 0.35μm CMOS 2P4M process and the TSMC 0.18μm SiGe BiCMOS process to realize light receiving and emitting devices. Under the illumination of laser at 850 nm, the measured responsibilities are 0.0310A/W, 0.0011A/W, and 0.2350A/W for device areas of 0.118mm×0.118mm, 0.124mm×0.124mm, and 0.72mm×0.60mm respectively. Moreover, an optical alignment experiment is carried out by using two of our chips, one operating in light emitting mode and the other in light receiving mode. The alignment sensitivity is 0.121μV/μm. Shih-hsiang Hsu Cheng-kuang Liu 徐世祥 劉政光 2012 學位論文 ; thesis 98 zh-TW
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description 碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === This thesis presents the design and realization of Si-based and SiGe-based optical receiving and light emitting integrated circuits, including limiting amplifier, burst-mode automatic gain controlled (AGC) transimpedance amplifier and light receiving and emitting device. First, the designs of transimpedance and limiting amplifier using the TSMC 0.18μm CMOS 1P6M process are made. The RGC-type input stage is used in the circuits. It effectively isolate input parasitic capacitance, and therefore increases bandwidth performance. By adding limiting amplifier, the output swing is raised and restricts output voltage to the logic level. At 1.8V and 0.25pF input capacitance to our design, the simulated bandwidth is 3.7GHz for a gain of 73.9dBΩ and a total power consumption of 58.2mW. Secondly, we present a design of a burst-mode receiving circuit using RGC-type TIA with AGC circuit and variable gain amplifier (VGA). We use the TSMC 0.18μm SiGe BiCMOS process. At 1.8V and 0.25pF input capacitance to our design, the simulated dynamic gain range, the corresponding dynamic bandwidth range, and the total power consumption are 58.6~77.2dBΩ, 2.5~3.6GHz, and 84.9mW respectively. Finally, we use the TSMC 0.35μm CMOS 2P4M process and the TSMC 0.18μm SiGe BiCMOS process to realize light receiving and emitting devices. Under the illumination of laser at 850 nm, the measured responsibilities are 0.0310A/W, 0.0011A/W, and 0.2350A/W for device areas of 0.118mm×0.118mm, 0.124mm×0.124mm, and 0.72mm×0.60mm respectively. Moreover, an optical alignment experiment is carried out by using two of our chips, one operating in light emitting mode and the other in light receiving mode. The alignment sensitivity is 0.121μV/μm.
author2 Shih-hsiang Hsu
author_facet Shih-hsiang Hsu
Po-hung Lin
林柏宏
author Po-hung Lin
林柏宏
spellingShingle Po-hung Lin
林柏宏
The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
author_sort Po-hung Lin
title The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
title_short The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
title_full The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
title_fullStr The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
title_full_unstemmed The Design and Implementation of Optical Communication and Optical Interconnection Integrated Circuits
title_sort design and implementation of optical communication and optical interconnection integrated circuits
publishDate 2012
url http://ndltd.ncl.edu.tw/handle/98141978414241815376
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