| Summary: | 碩士 === 東海大學 === 電機工程學系 === 100 === With the rapid progress of design technology, the use of SoC is increasingly widespread. SoC contains a huge number of Silicon IP (SIP) modules, and the SIP modules often use on-chip buses to transmit the data or control signals. However, the problems of communication latency, circuit synchronization, signal noise and power consumption need to be improved due to narrowing process. To ensure the accuracy of data communication between each module, the network packet transmission concept is applied to on-chip communication, which is called Network-on-Chip (NoC) design.
NoC is a flexible and reliable on-chip communication architecture. 2D mesh topology is often used for NoC design, because it can use a simple routing algorithm, and has good scalability. However, the 2D mesh topology has relatively large radius of the network, and causes larger transmission delay for long distance packets. In this paper, we propose an improved design for 2D mesh topology. The main concept is long distance data transmission take another layer of mesh to achieve fast communication goal.
The experimental results show that the multi-level mesh architecture can save 50% power, and improve 70% performance with 20% area increase.
Keyword：System-on-Chip ( SoC ), Network-on-Chip( NoC ), mesh, router design, Silicon IP (SIP)
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