A LOW POWER TUNABLE SC DOUBLE-SAMPLING THREE-BIT FOURTH-ORDER BANDPASS NOISE-COUPLING DELTA-SIGMA MODULATOR

• Main Authors: Ching-Jen Cheng, 鄭景仁
• Other Authors: Shu-Chuan Huang
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/85407781352121940462

碩士 === 大同大學 === 電機工程學系(所) === 100 === In this thesis, we propose a double-sampling three-bit fourth-order bandpass noise-coupling delta-sigma modulator. The design is based on a tunable resonator, which requires only one opamp and therefore has low power consumption. The double-sampling switched-capacitor (SC) technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. The active adder with noise coupling could avoid any signal attenuation due to parasitic, and kick-back noise from the quantizer, and improve two bit resolution in this modulator. The tunable resonator increases the resolution by properly adjusting the resonator frequency. In additional, we design a filter-based data-weighted averaging (DWA) to modify the harmonic tones caused by the mismatch errors of the capacitors in the internal DAC. This design is carried out as follows: First, The MATLAB and SIMULINK are used to ensure the stability and performance of the architecture. Then, the transistor level simulation is done by Hspice in TSMC 0.18um CMOS 1P6M process. At last, we implement this modulator at 1.5 voltage supply, 80MHz clock frequency and the center frequency of the input signal is 20MHz. The simulated SNDR is 48.39dB with -4.2dBFS for 5MHz bandwidth and the power consumption is 30.6mW.