Design and Analysis of Via Configurable Routing Fabrics

• Main Authors: Hsin-Pei Tsai, 蔡欣霈
• Other Authors: 林榮彬
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/16197243968383701681

碩士 === 元智大學 === 資訊工程學系 === 100 === With the advances in integrated circuit(IC) technology, the costs of designing and manufacturing ICs increase dramatically. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce IC design and manufacturing cost, structured ASIC emerges as a new design alternative. Structured ASIC consists of prefabricated transistors and prefabricated masks for some metal layers, and a few un-customized mask layers for vias. The logic in a structured ASIC is implemented using a basic logic block called via-configurable logic block (VCLB). The designers need only to customize a few via masks to complete the logic implementation and share the prefabricated mask cost. Structured ASIC router is an important tool to via-configurable structured ASICs. A structured ASIC router employs a via-configurable routing fabric (VCRF) to complete routing. Without such a router, structured ASIC will not become a viable technology. In this thesis, we present a method for design and analysis of VCRFs. We find that the trade-off between wire length and via count is a good metric for qualifying a VCRF. It can be used along with the degree of reduction in average routing resource per internal net in a VCRF to determine which VCRF is better. This metric is validated by full-chip routing and has been successfully used to create better routing fabrics.