| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 100 === Due to the fact that analog circuits are usually very sensitive, it is desirable to consider parasitic effects early in the design flow. For instance, in the design of an analog circuit, it is possible that the result of post-layout simulation does not conform to the result of pre-layout simulation because of layout-induced effects. In order to solve the problem, many layout-aware analog circuit design methodologies have been proposed in the literature.
In a layout-aware analog circuit design flow which is based on the use of parameterized layouts, parasitics can be estimated early in the design flow if models of extracted circuits can be generated from parameterized layouts. In order to perform circuit extraction from parameterized layouts, algorithms are required for dealing with parameterized polygons which reside in parameterized layouts. In particular, we must be able to perform Boolean operations on parameterized polygons.
In this thesis, we propose an efficient approach for performing Boolean mask operations on parameterized 45-degree polygons. The approach involves using an MILP (mixed integer linear programming) solver to find a feasible solution and then transform input parameterized polygons into fixed-coordinate polygons. As a result, Boolean operations can be performed efficiently on these fixed-coordinate polygons. By using proper data structures, the resultant fixed-polygons can be transformed into parameterized polygons rapidly. The proposed approach can be applied to algorithms for performing Boolean operations including AND, OR, NOT, and XOR operations.
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