| Summary: | 碩士 === 元智大學 === 通訊工程學系 === 100 === The design and implementation of the voltage multiplier in the rectifier antenna (rectenna) is studied in this thesis. The basic theory of the voltage multiplier is first reviewed and followed by the design and implementation of the single-stage voltage multiplier. The proposed voltage multiplier is comprised of the impedance matching circuit using the microstrip lines, the Schottky diode circuit, and the RC load circuit. The RC load circuit includes a 100 pF capacitance as an output filter and resistance of 50 Ohm as an output load resistor. The target input powers for the voltage multiplier are 0dBm, -10dBm, -20dBm and -30dBm at 2.45GHz. The single-stage voltage multiplier is designed using the ADS software and the reflection coefficients are measured by the Agilent E5071B. The output powers of the proposed circuit are then measured by using a signal generator as the input source and a oscilloscope as the output monitor. The Schottky diode is not operated when the input power is less than -20dBm and the circuit basically is not working at this point. On the contrary, the most output powers of the proposed multiplier are around 45mV if the designed input power is employed. The conjugate impedance matching between the input and output ports should be applied to lift the efficiency from the current value, 15%.
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